Technical Field
Embodiments described herein relate to the field of integrated circuit design and more particularly, to semiconductor area optimization.
Description of the Related Art
The semiconductor industry aims to manufacture integrated circuits with higher and higher densities of semiconductor devices on a smaller chip area to achieve greater functionality and to reduce manufacturing costs. This desire for large scale integration has led to a continued shrinking of circuit dimensions and device features. The ability to reduce the size of structures is driven by lithographic performance.
With conventional photolithography systems, radiation is provided through or reflected off a mask or reticle to form an image on a semiconductor wafer. Generally, the image is focused on the wafer to expose and pattern a layer of material, such as photoresist material. In turn, the photoresist material is utilized to define doping regions, deposition regions, etching regions, or other structures and features in one or more layers of the semiconductor wafer. The photoresist material can also define conductive lines or conductive pads associated with metal layers of a semiconductor device. Further, the photoresist material can define isolation regions, transistor gates, or other transistor structures and elements.
A multiple exposure/pattern process utilizes two or more photolithographic sub-processes and two or more photomasks and can be used to form patterns of extremely small and tightly packed features. A pitch or distance between lines on a photomask must be greater than a certain amount for a given wavelength and aperture of a lens used in the photolithographic process. Downward scaling of pitch or line separation is ultimately limited by the practical performance capabilities of the photolithographic tools. Consequently, certain design rules are commonly used to check the viability and manufacturability of desired semiconductor device features. For example, design rule check (DRC) methodologies can be applied to identify potential spacing violations in a proposed layout of conductive traces, such as local interconnects. Thus, if the proposed layout includes spacing that is too short for the particular photolithographic tool, then it may not be possible to fabricate devices using that proposed layout without shorting some conductive traces together.